1. Field of the Invention
The present invention relates to a charge pump circuit and, more particularly, to a so-called charge pump circuit for outputting a signal having a boosted voltage higher than the voltage supplied from outside of the circuit.
2. Description of the Related Art
A conventional charge pump circuit in a semiconductor device has a configuration such as shown in FIG. 1. A first N-channel MOS transistor (hereinafter referred to as simply an "NMOS transistor") 36 is connected between a VCC line 11 and an internal charge-up node 17. A second NMOS transistor 37 is connected between the internal charge-up node 17 and an output terminal 12. The internal charge-up node 17 is connected via a capacitor element 18 to a CMOS inverter 19, which receives a clock signal. The charge pump circuit has a function of boosting a supply voltage to output a higher voltage to an external load while receiving a regularly varing signal such as a clock signal.
In operation, when the potential of the clock signal input to the CMOS inverter 19 rises, the potential at the internal charge-up node 17 rises due to the capacitive coupling by the capacitor element 18. At this time, if the potential at the output terminal 12 is lower than the potential at the internal charge-up node 17, current flows from the internal charge-up node 17 to the output terminal 12 through the second NMOS transistor 37, so that a load (not shown in the drawing) connected to the output terminal 12 is provided with charge.
When the potential of the clock signal subsequently rises and the potential at the internal charge-up node 17 falls accordingly due to the capacitive coupling of the capacitor element 18, the charge lost from the input charge-up node 17 to the load is replenished from the VCC line 11 via the first NMOS transistor 36. In cases where the parasitic capacitance existing between the internal charge-up node 17 and ground is significantly small as compared to the capacitance of the capacitor element 18 and the amount of current required to charge the load is small, the potential at the internal charge-up node 17 rises to a potential which is lower than double the power-supply voltage by the threshold voltage V.sub.T of the first NMOS transistor 36, when the clock signal falls. Accordingly, in an ideal state of the circuit, the potential at the output terminal 12 reaches a potential which is determined by subtracting, from twice the magnitude of the power-supply voltage, the sum of the threshold voltage V.sub.T36 of the first NMOS transistor 36 and the threshold voltage V.sub.T3 of the second NMOS transistor 37.
Since each of the first and second NMOS transistors 36 and 37 has a so-called diode connection, substantially no current flows through the output terminal 12 into the internal charge-up node 17. In practical cases, the gates of the first and second NMOS transistors 36 and 37 are formed to have a large width to sufficiently lower their resistance in an ON state. Namely, the NMOS transistors are designed such that the diffusion capacitances and the gate capacitances of the NMOS transistors 36 and 37 are large.
The conventional charge pump circuit as described above, however, can only boost voltage within a limited range, as will be detailed later.